1. Field of the Invention
The present invention relates to an arrangement for the equipping of electronic packages with elliptical C4 connects possessing optimal orientation for enhanced reliability. Furthermore, the invention is also directed to a method providing elliptical C4 connects which possesses optimal orientation for enhanced reliability, as implemented in connection with their installation in electronic packages.
An electronic package for a computer may be assembled by connecting a microprocessor chip, for instance, possessing typical dimensions of about 15×15 mm to a substrate of about 50×50 mm in size. The chip is typically made of silicon, whereas the substrate is most frequently constituted of a composite structure, having several layers of copper lines and planes embedded in a polymeric matrix, which is broadly referred to as “resin”. The electrical connection between the microprocessor chip and the substrate is formed by an operatively guaranteed by an array of solder joints referred to as C4s (Controlled Collapse Chip Connections). Each C4 brazes or solders a metal pad on the bottom surface of the chip to a respective symmetrical pad, which is located on the top surface of the substrate, wherein the C4 brazing process is identified as the reflow. During reflow, the package and the C4s are subjected to a temperature which is higher than the melting point of the solder material (about 185° C.-230° C.); whereby a few minutes of exposure to this temperature range is typically adequate to achieve a good electrical and mechanical connection between the components. The resulting shape of the C4s, as described hereinbelow in more specific detail, is governed by the shape of the pads.
The solder material, which is normally constituted of tin/lead (Sn/Pb) or tin/silver/copper (Sn/Ag/Cu—SAC), is known to be subject to a finite fatigue life when subjected to a cyclical strain, whereby in the field, the cyclical strain encountered in the C4s is the result of thermal cycles sustained by the electronic package; in which the chip and substrate have different coefficients of thermal expansion (CTE), and upon being exposed to temperature variations, their respective materials deform differently, consequently shearing and destroying the C4s. In order to reduce the shear strain, which is applied to the C4s, a layer of an underfill material is added so as to bind the chip and the substrate following the first or initial reflow process. The underfill material significantly reduces the relative motion between the chip and the substrate surfaces, thereby forcing the overall assembly to bend. Bending stresses are much more benign than shear stresses for the C4 connects, which will result in an enhanced reliability and mechanical robustness or strength of the electronic package.
2. Discussion of the Prior Art
Pertaining to the present state-of-the-technology, this is elucidated on the basis of FIGS. 1(a) through 1(c) of the drawings, illustrative of silicon chips mounted on a substrate by employing current types of C4 connections.
A schematic of a silicon chip mounted on a substrate is depicted in FIG. 1(a) plan view; FIG. 1(b) in a cross-sectional view; and FIG. 1(c) in a close-up on one C4, shown enlarged, whereby the chip is connected to the substrate through the C4s. The circular shape of the pads, which are embedded in both the chip and the substrate represents a guarantee that the C4 will have two circular faces; whereby this aspect, together with the bulging profile deriving from the reflow process, imparts to the C4 a nearly spherical shape, as shown in FIG. 1(c). Hereby, a typical C4 may possess a diameter of about 120 μm at its center, and about 100 μm at the joints, with a height of about 100 μm. In a widely adopted industry standard (‘4 on 8’), C4s with 100 μm pad diameter are distributed on a square grid with a pitch of 200 μm. The industry trend is to reduce the C4 diameter and distribution pitch so that the joint density necessary for high input/output (I/O) connections can be increased. As an example, the industry is also investigating the performance of micro-C4s with 25 μm diameter pads, 10-20 μm heights and a pitch of 50 μm.
The chip-substrate assembly has to survive not only temperature cycles in the field, but also standard deep thermal cycles (DTC) before shipment. Under both environments, the differential motion between the chip and the substrate induces a shear strain in the C4, as described hereinabove; concerning which, an encountered shear strain in excess of a threshold value (typically 0.1%) results in plastic deformation, whereby repetitive strain cycles with plastic deformation lead to a cumulative damaging process, which eventually culminates in fatigue failure of the C4s at a relatively low number of cycles, typically between 1000 to 2000. The C4s, which are located furthest from the chip's neutral point (distance from neutral point—DNP) undergo the largest strain during thermal cycling and are known to fail first, leading to the conclusion that an increase in chip size is bound to reduce the service life expectancy of a C4 chip joint.
The number of cycles to failure (N) at a given temperature is represented approximately by an empirical formula, motivated by Coffin/Manson about 50 years ago; as follows:N=c/(Δen)
The constant c and exponent n (˜2) are material-dependent, whereas Δe represents the plastic deformation encountered during a cycle. During most of the time in a DTC, the temperature of the solder is high enough for the C4s to creep. Inclusion of this effect results in a more complex formulation; however, the fundamental observation is that a reduction in plastic strain results in a substantial (non-linear) improvement in the number of cycles up to failure.
In particular, pursuant to the prior art, there is described a method of analyzing solder shapes after reflow, wherein problems are addressed with regard to comparison between elliptical and round solder pads. Hereby, this aspect is treated in an article by Kuo-Ning Chiang, et al., entitled “A Comparison of Thermal Stress/Strain Behavior of Elliptical/Round Solder Pads”, Journal of Electronic Packaging, June 2001, Volume 123, Pages 127-131.